1. Field of the Disclosure
The present disclosure relates to a display device, and more particularly, to a display device and a method of manufacturing the same.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, many efforts and studies are being made to develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, field emission displays, organic electroluminescence display (OELD) devices and the like, as a substitute for CRTs. Recently, active matrix type LCD devices, PDP devices, OELD devices and the like have been widely used. The active matrix type display devices include a TFT substrate, which is referred to as an array substrate, and the array substrate includes a plurality of thin film transistors formed in a plurality of pixels, respectively.
FIG. 1 is a cross-sectional view illustrating an array substrate for a display device according to the related art. For example, FIG. 1 shows an array substrate of an LCD device among display devices.
Referring to FIG. 1, the array substrate includes a gate line and a data line 33 crossing each other on a substrate 11 to define a pixel region P. A thin film transistor Tr is connected to the gate line and the data line 33. The thin film transistor Tr is formed in a switching region TrA. The thin film transistor Tr includes a gate electrode 15, a semiconductor layer 28, and source and drain electrodes 36 and 38. The semiconductor layer 28 includes an active layer 22 made of intrinsic amorphous silicon and both ohmic contact layers 26 made of extrinsic amorphous silicon. A gate insulating layer 18 is formed on the gate line and the gate electrode 15. A passivation layer 42 is formed on the thin film transistor Tr and includes a drain contact hole 45 exposing the drain electrode 38. A pixel electrode 50 is formed on the passivation layer 42 and contacts the drain electrode 38 through the drain contact hole 45.
A semiconductor pattern 29 is formed below the data line 33. The semiconductor pattern 29 includes a first pattern 23 made of intrinsic amorphous silicon and a second pattern 27 made of extrinsic amorphous silicon.
In the related art array substrate, a portion of the active layer 22 below the ohmic contact layers 26 has a thickness t2 more than a thickness t1 of a portion of the active layer 22 between the ohmic contact layers 26. This thickness difference is caused by a manufacturing process, and due to the thickness difference, a property of the thin film transistor Tr is degraded.
FIGS. 2A to 2E are cross-sectional views illustrating forming the thin film transistor of FIG. 1. For convenience' sake, FIGS. 2A to 2E does not show the gate electrode and the gate insulating layer.
Referring to FIG. 2A, an intrinsic amorphous silicon layer 20, an extrinsic amorphous silicon layer 24 and a metal layer 30 are formed on a substrate 11. Then, a photoresist pattern is formed on the metal layer 30. The photoresist pattern includes first portions 91 and a second portion 92, and the first portions 91 are at both sides of the second portion 92. The first portions 91 have a thickness more than the second portion 92.
Referring to FIG. 2B, the metal layer (30 of FIG. 2A), the extrinsic amorphous silicon layer (24 of FIG. 2A) and the intrinsic amorphous silicon layer (20 of FIG. 2A) are etched using the photoresist pattern to form a source-drain pattern 31, an extrinsic amorphous silicon pattern 25 and an active layer 22.
Referring to FIG. 2C, an ashing process is performed to remove the second portion (92 of FIG. 2B). The first portions 91 are partially removed and the thickness of the first portions 91 decreases.
Referring to FIG. 2D, the source-drain pattern (31 of FIG. 2C) is etched using the ashed photoresist pattern to form source and drain electrodes 36 and 38 spaced apart from each other.
Referring to FIG. 2E, a portion of the extrinsic amorphous silicon pattern (25 of FIG. 2D) between the source and drain electrodes 36 and 38 is dry-etched to form ohmic contact layers 26 below the source and drain electrodes 36 and 38, respectively. The dry-etching process continues enough to completely remove the portion of the extrinsic amorphous silicon pattern between the source and drain electrodes 36 and 38, and thus, a portion of the active layer 22 between the source and drain electrodes 36 and 38 is etched to a predetermined extent. Accordingly, the portion of the active layer 22 between the source and drain electrodes 36 and 38 has a thickness t1 less than a thickness t2 of a portion of the active layer 22 below the ohmic contact layers 26. If the dry-etching process is not performed enough, the extrinsic amorphous silicon pattern might remain on the portion of the active layer 22 between the source and drain electrodes 36 and 38. To prevent this, the dry-etching process continues to be performed until the active layer 22 is partially removed.
However, such a dry-etching process causes the active layer 22 not to be uniform. Further, the portion of the active layer 22 between the source and drain electrodes 36 and 38 to be damaged by the dry-etching. Accordingly, a property of the thin film transistor is degraded.
Further, since the active layer 22 is made of amorphous silicon, an electric property of the thin film transistor is not excellent. For example, a mobility of the active layer 22 is as low as about 0.1 cm2/V·s to 1.0 cm2/V·s. Accordingly, there is a limit in employing the amorphous silicon active layer 22 into a thin film transistor for a driving circuit.
A polycrystalline silicon type thin film transistor has been proposed, which is manufactured by crystallizing an amorphous silicon layer using a laser apparatus. FIG. 3 is a cross-sectional view illustrating an array substrate, including a polycrystalline silicon type thin film transistor, for a display device according to the related art.
Referring to FIG. 3, an active layer 55 on a substrate 51 is made of polycrystalline silicon and includes an active portion 55a, and source and drain portions 55b and 55c at both sides of the active portion 55a. The source and drain portions 55b and 55c are doped with n+ or p+ ions. To dope the source and drain portions 55b and 55c, an ion implantation apparatus is additionally required. This causes production costs and processes to increase. Further, since the ion implantation apparatus is newly added, manufacturing apparatuses and processes for the array substrate should be newly configured.